Brandon's Bytes

Project: lc3-hw [2]: The reference CPU design

28 Jun 2018

This post is a copy from my old website and blog. I have kept its original post date.

In the last post, I looked at putting together some building blocks to use when I work on the actual LC-3 bits.

In this post I’ll discuss implementing the reference design found in Appendix C Figure C.8 of Introduction to Computing Systems 2nd Ed.

First I needed to draw out what exactly encompasses the “CPU” proper: for the purposes of this project I interpreted the “CPU” as all the logic that the bus (the big black double ended arrow) wraps around. I decided to make the memory related blocks and the interrupt related blocks outside of the bus separate parts in the LC-3 system overall, which I’ll discuss in the next post: the reference CPU is more of and easily addressable low-hanging fruit. The control signals that deal with these blocks were simply made outputs from the CPU to go to the respective memory and interrupt controller modules.

Since the block diagram for all the components of the CPU are already there (albeit some structures are in separate figures), the implementation was more or less straightforward. The modules written in the previous post came quite in handy: the tristate buffer module was used for gating values to the bus and the ROM module was used to hold the microcode.

That being said, it doesn’t seem that Dr. Patt really explained/specified some parts of the interrupt logic: how the device represents priority (and what happens when multiple interrupts occur from multiple devices) isn’t specified nor is the origin of the LD.Priority signal explained (with no column for it in the Official Microcode Table found at the end of Appendix C and not being counted in the total control signal count). To deal with the LD.Priority signal, I’ve hardwired it as a function of other realted control signals like LD.CC.

I haven’t written out the microcode for it yet (I did not have the pleasure of taking EE 306 with Dr. Patt, so I didn’t have to do this as a freshman), so it’s more or less non-functional and non-testable. I’ll get to this at some point.

Source code for the CPU module can be found here.