10 Feb 2018
This post is a copy from my old website and blog. I have kept its original post date.
So in the labs for the UT class EE 460N (Computer Architecture) we have to make a cycle-level, block-diagram accurate C implementation of Dr. Yale Patt’s LC-3b ISA as well as implement additional features such as interrupt processing and virtual memory.
What irked me was that we had to ustilize ANSI C in ONE. SINGLE. FILE. instead of using some HDL.
To rectify this, I’m going to do implementations of the original LC-3 ISA as specified by Patt’s Introduction to Computing Systems, 2nd Ed. in structural Verilog and see if I can get it all the way to be put onto an FPGA.
Follow the project’s code here.